The present invention relates to a semiconductor memory device, and more particularly to a semiconductor memory device which controls the voltage supplied to a dummy bit line and a biasing method thereof.
In general, a semiconductor device utilizes a dummy bit line that is not intended for performing operational functions but for the purposes of advantageous manufacturing processes. These process advantages can be largely divided into two types.
First, it is possible to compensate a height difference in a vertical section between a cell array area and a peripheral circuit area. Second, it is possible to realize an environment similar to that in which normal bit lines are repeated in the edges of a normal cell array area since the edges of the normal cell array area are weak.
FIG. 1 illustrates a cell array of a general memory device including a dummy bit line and FIG. 2 illustrates a voltage applying unit which applies a voltage to the dummy bit line.
In general, a semiconductor memory device includes a memory cell array block having a plurality of unit memory cells connected to a word line and a bit line to store data, a bit line isolation unit which isolates and connects the bit line and a bit line sense amplifier, an equalization/precharge unit which precharges a bit line pair and maintains equal voltage levels in the bit line pair, and the bit line sense amplifier which senses and amplifies a difference in the voltage levels between the bit line pair. FIG. 1 illustrates a layout of the memory cell array block of the semiconductor memory device in which only an active area and node contacts are shown and units not in direct relation to the present invention are not shown.
Referring to FIG. 1, a memory cell array is formed with an active area 10 and the active area 10 is formed with a storage node landing plug contact (LPC) a bit line node LPC and a bit line node contact thereon.
The LPCs are contacts which are firstly perforated in a silicon substrate and it should not be electrically shorted with a gate material upon contact. The generation of the short causes many problems, which will be described herein.
An operation in which a bias is applied to bit lines BL and BLb and a dummy bit line DBL will be described with reference to FIG. 2.
Referring to FIG. 2, the semiconductor memory device is formed with an upper bit line precharge/equalization unit 10, an upper bit line isolation unit 20, a bit line sense amplifier 30, a column selection unit 40, a lower bit line isolation unit 50 and a lower bit line equalization unit 60 between an upper cell array 1 and a lower cell array 2.
The upper bit line precharge/equalization unit 10 is provided with NMOS transistors N3 and N4 which precharge the bit line pair BL and BLb to a bit line precharge voltage VBLP (generally, Vdd/2) using a bit line equalization signal BLEQ as a gate input and an NMOS transistor N0 which equalizes the bit line pair BL and BLb using the bit line equalization signal BLEQ as a gate input.
The upper bit line isolation unit 20 is for selectively isolating the bit line sense amplifier 30 and the bit line pair BL and BLb of the upper cell array 1, and includes two NMOS transistors N1 and N2 which use an upper bit line isolation signal BISH as a gate input.
The bit line sense amplifier 30 is for amplifying data on the bit line pair and, although there exists various types, is generally provided with two PMOS transistors connected between a pull-up power source RTO and the bit line pair and two NMOS transistors connected between a pull-down power source Sb and the bit line pair.
The column selection unit 40 selectively connects the bit line pair BL and BLb and segment data bus pair SIO and SIOb in response to a column selection signal CY.
The lower bit line isolation unit 50 is for selectively isolating the bit line sense amplifier 30 and the bit line pair BL and BLb of the lower cell array 2, and includes two NMOS transistors N5 and N6 which use a lower bit line isolation signal BISL as a gate input.
The lower bit line equalization unit 60 includes an NMOS transistor N7 which equalizes the lower bit line pair using the bit line equalization signal BLEQ as a gate input.
In the above described structure, when an active command is applied, the bit line equalization signal BLEQ is inactivated to a logic level “low” to turn off the NMOS transistors N0, N3, N4 and N7. Therefore, the bit line pair is floated from the precharge voltage VBLP. At this time, the normal bit line is in a state of being floated with the precharge voltage VBLP but the dummy bit line is continuously supplied with the precharge voltage VBLP since the dummy bit line is in direct connection with the precharge voltage VBLP. In other words, the precharge voltage VBLP is applied not to the normal bit line BL but to the dummy bit line DBL when the active command is applied. Such a biasing method causes many problems as the size of a sub word line is decreased.
These problems will be described with reference to FIG. 3.
FIG. 3A illustrates a case that a LPC short 31 is generated between a dummy bit line and a word line; FIG. 3B illustrates a case that a LPC short 32 is generated between a storage node a and a word line when a MOS transistor is on; and FIG. 3C illustrates a case that a LPC short 33 is generated between a word line of a data cell which is not selected and a storage node a.
In the cases in which the aforementioned short is generated upon application of an active command, as shown in FIGS. 3A and 3B, an enabled word line voltage VPP and a precharge voltage VBLP applied to the dummy bit line are in conflict with each other to lower the word line voltage VPP.
Also, when a precharge command is applied, as shown in FIG. 3C, a disabled word line voltage VSS and a precharge voltage VBLP applied to the dummy bit line are in conflict with each other to raise the word line voltage VSS.
This LPC short may cause many problems. For example, when the word line voltage VPP is lowered due to the short as shown in FIGS. 3A and 3B, the write recovery time (tWR) worsens. Also, when the voltage of the word line in which a ground voltage level should be maintained is raised as shown in FIG. 3C, a defect is generated creating unnecessary current flow.